A phase-locked loop (PLL) circuit feedback-controls a controlled oscillator so that an oscillation signal generated by the controlled oscillator (or a signal with a frequency which is one-Nth of the frequency of the oscillation signal) has a frequency and a phase equal to the frequency and phase of a reference signal. Here, N denotes the frequency ratio of a desired signal to the reference signal. N may be an integer or a real number including an integer portion and a fractional portion. As the controlled oscillator provided in the PLL circuit, for example, a ring oscillator is used. The ring oscillator is sensitive to a power supply voltage. Thus, phase noise characteristics of the PLL circuit comprising the ring oscillator is likely to be degraded by power supply noise applied to the power supply voltage.
A combination of the power supply for the ring oscillator with a low-dropout (LDO) regulator enables the power supply noise immunity of the PLL circuit to be improved. However, disadvantageously, the use of the LDO regulator requires a capacitor which suppresses the power consumption of the LDO regulator and high-frequency noise from the LDO regulator.
The use of a power supply noise canceller also enables the power supply noise immunity of the PLL to be improved. The power supply noise canceller is formed using an analog circuit, and thus variations in parameters for the power supply noise canceller are preferably compensated for by calibration. Specifically, convergence of the PLL is followed by activation of a power supply noise cancellation loop including the power supply noise canceller. The convergence of the power supply noise cancellation loop completes the calibration of the power supply noise canceller. The calibration appropriately compensates for variations in the parameters for the analog circuit forming the power supply noise canceller, allowing the power supply noise canceller to function accurately. Hence, the frequency of the oscillation signal is robust against the power supply noise. In contrast, time required for the calibration delays the activation of the PLL circuit.